During ESD, large currents may flow through an IC which may potentially cause damage. Damage may occur within the device that conducts the current, as well as in devices that see a significant voltage drop due to the large current flow. To avoid damage due to an ESD event, clamps are added to the IC. These clamps may shunt the large ESD current without causing high voltage over sensitive nodes of the IC.
An example of an ESD clamp 100 is depicted in FIG. 1. The ESD clamp 100 comprises a silicon controlled rectifier (SCR) which may be formed by a PNP transistor 103 and an NPN transistor 104. This clamp may trigger from a well-to-well breakdown and may clamp at a low voltage such as 1V to 2V. The current caused by the avalanching the base-collector junction of the PNP 103 and collector-base junction of the NPN 104 may flow through the emitter-base of the PNP 103 and base emitter of the NPN 104. Positive feedback may be established, which may be the origin of the low holding voltage of the ESD clamp 100. Advantages of ESD clamp 100 may include a low clamping voltage, low on-resistance and a high failure current. However, ESD clamp 100 may shunt current during normal operating conditions, which may result in temporary loss of function. To restore normal operation, human or other IC interaction may be required. Further, if ESD clamp 100 triggers and enters into a low conductive (shunt) mode during normal operation, the energy of the current through the ESD clamp 100 may be too high such that temporary or permanent damage to the IC may occur. Such an increased (supply) current during normal operation, often caused by faulty triggering of the ESD clamp, may be called a latch up (LU) event.
A known way to overcome these issues may be to design ESD clamps with a high holding voltage. The holding voltage of the clamp may be the lowest voltage at which the device may sustain its high conductivity regime. By increasing the holding voltage above the supply level, the ESD clamp may be guaranteed to release from a latched/shunt state even if it is triggered during normal operation. As such, the loss of function may be temporary. Examples of such clamps include Zener diodes, and gate-grounded N-type metal oxide semiconductors (GGNMOS). These clamps may have a high clamping voltage but may also fail at a low current and their on-resistance may be high. Moreover, to comply with ESD requirements, a large chip area may be consumed to form these clamps.
A further requirement for an ESD protection clamp may include a low standby or leakage current. For some applications, the amount of capacitance added to the pad to which the ESD clamp is coupled may be minimized as well.
Therefore, there is a need for an improved ESD protection clamp, which combines the advantages of high and tunable holding voltage, low leakage, high and tunable trigger voltage, small silicon area for high current capability, and fast and effective triggering.